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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a complete 12-bit, 3 msps monolithic a/d converter ad1672 ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features single supply pin configurable input voltage ranges power dissipation: 240 mw no missing codes guaranteed differential nonlinearity error: 0.5 lsb complete: on-chip sample-and-hold amplifier and voltage reference signal-to-noise and distortion ratio: 68 db spurious-free dynamic range: C77 db out of range indicator binary output data digital i/os compatible with +5 v or +3.3 v logic 28-pin plcc package input combined with the power and cost savings over previously available solutions will enable new designs in communications, imaging and medical applications. the ad1672 provides both reference output and reference input pins allowing the onboard reference to serve as a system reference. an external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. the digital output data is pre- sented in a straight binary output format for the unipolar input ranges of 0 v to 2.5 v and 0 v to 5.0 v. for the bipolar input range of C2.5 v to +2.5 v, the digital output data is presented in an offset binary format. an out-of-range (otr) signal indicates an overflow condition. it can be used with the most significant bit to determine low or high overflow. the ad1672 is packaged in a 28-pin plcc package and is specified for operation from C40 c to +85 c. product highlight the ad1672 offers a complete single-chip sampling 12-bit, 3 msps analog-to-digital conversion function in a 28-pin plcc package. the ad1672 at 240 mw consumes a fraction of the power of presently available solutions and provides exceptional perfor- mance relative to other monolithic solutions. out of range (otr)the otr output bit indicates when the input signal is beyond the ad1672s input range. ease-of-usethe single supply ad1672 is complete with sha voltage reference and pin strappable input ranges. it is compat- ible with a wide range of amplifiers. product description the ad1672 is a monolithic, single supply 12-bit, 3 msps analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier (sha) and voltage reference. the ad1672 uses a multistage pipelined architecture with output error correction logic to provide 12-bit accuracy at 3 msps data rates and guarantees no missing codes over the full operating temperature range. the ad1672 combines a high performance bicmos process and a novel architecture to achieve its high performance levels. the fast settling input sha is equally suited for both multi- plexed systems that switch negative to positive full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to the nyquist rate. the ad1672s wid eband functional block diagram tha tha dac amp ref amp 4 4 3 4 correction logic 2.5v ref output refcom output data 12 bits clock input adc dac adc bandgap reference latches clock timer noise reduction ain1 & 2 ref in ad1672 tha tha refcom adc dac adc dac obsolete
ad1672Cspecifications dc specifications rev. 0 C2C (t min to t max with v cc = +5.0 v, v dd = +5.0 v, drv dd = +5.0 v, f sample = 3 mhz unless otherwise noted) ad1672ap parameter min typ max units resolution 12 bits max conversion rate 3 mhz accuracy integral nonlinearity (inl) C2.5 1.0 2.5 lsb differential nonlinearity (dnl) C1.0 0.5 1.5 lsb no missing codes 12 bits guaranteed offset error C0.75 0.20 0.75 % fsr zero error 1 C0.75 0.20 0.75 % fsr gain error 2 C1.50 0.30 1.50 % fsr power supply rejection 3 v cc (5.0 v 0.25 v) C0.30 0.30 % fsr v dd (5.0 v 0.25 v) C0.30 0.30 % fsr v drdd (3.0 v to 5.25 v) C0.10 0.10 % fsr analog input input ranges 2.5 v range unipolar 0.0 2.5 volts 5.0 v range unipolar 0.0 5.0 volts 5.0 v bipolar C2.5 2.5 volts input resistance 2.5 v input range 1.5 2.0 2.5 k w 5.0 v input ranges 3.0 4.0 5.0 k w input capacitance 10 pf internal voltage reference output voltage 2.475 2.5 2.525 volts output current 4 0.5 ma reference input resistance 6.0 8.0 10.0 k w power supplies supply voltages v cc 4.75 5.0 5.25 volts v dd 4.75 5.0 5.25 volts drv dd 3.00 5.0 5.25 volts supply current i vcc 46 65 ma i vdd 1.0 2.0 ma i drvdd 0.2 2.0 ma power consumption 240 363 mw temperature range C40 25 85 c notes 1 bipolar mode. 2 includes internal reference error. 3 change in full scale as a function of the dc supply voltage. 4 current available for external loads. external load should not change during conversion. specification subject to change without notice. obsolete
ac specifications ad1672ap parameter min typ max units signal-to-noise and distortion ratio (s/(n+d)) f input = 100 khz 68 db f input = 500 khz 63 68 db f input = 1.5 mhz 60 db signal-to-noise ratio (snr) f input = 100 khz 70 db f input = 500 khz 66 70 db f input = 1.5 mhz 67 db total harmonic distortion (thd) f input = 100 khz C74 db f input = 500 khz C74 C64 db f input = 1.5 mhz C60 db spurious free dynamic range (sfdr) f input = 100 khz C77 db f input = 500 khz C77 C65 db f input = 1.5 mhz C61 db intermodulation distortion (imd) 1 65 db full power bandwidth 5 mhz small signal bandwidth (C20 db fsr) 20 mhz code transition noise 1/4 lsb rms aperture delay 9 ns aperture jitter 10 ps rms acquisition to full-scale step 150 ns overvoltage recovery time 150 ns notes 1 fs = 490 khz; fb = 510 khz typical value for third order products. specifications subject to change without notice. digital specification ad1672ap parameter symbol min typ max units logic inputs high level input voltage v ih 3.5 volts low level input voltage v il 1.0 volts high level input current (v in = v dd )i ih C10 10 m a low level input current (v in = 0 v) i il C10 10 m a input capacitance c in 10 pf logic outputs high level output voltage (i oh = 0.5 ma) v oh 2.4 volts low level output voltage (i ol = 1.6 ma) v ol 0.4 volts output capacitance c out 5pf specifications subject to change without notice. (t min to t max with v cc = +5 .0 v, v dd = +5.0 v, drv dd = +5.0 v, f sample = 3 mhz, ain = 0.5 db in bipolar C2.5 v to +2.5 v configuration unless otherwise noted) ad1672 rev. 0 C3C (t min to t max with v cc = +5 .0 v, v dd = +5.0 v, v drvdd = +5.0 v unless otherwise noted) obsolete
ad1672 rev. 0 C4C t od s1 s1 s2 s2 s3 s3 data 1 data 2 analog input input clock data output otr t c t cl t ch figure 1. timing diagram switching specifications parameter symbol value units clock period t c 334 ns min clock pulse width high t ch 167 ns min pulse width low t cl 167 ns min output delay t od 15 ns min 30 ns typ pipeline delay (latency) 2.5 clock cycles absolute maximum ratings* parameter with respect to min max units v cc acom C0 5 +6.5 volts v dd dcom C0.5 +6.5 volts drv dd drcom C0.5 +6.5 volts acom dcom, drcom C0.5 +0.5 volts clock dcom C0.5 v dd + 0.5 volts digital outputs dcom C0.5 drv dd + 0.5 volts ain acom C6.5 +6.5 volts refin acom C0.5 v cc + 0.5 volts junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad1672 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. obsolete
ad1672 rev. 0 C5C pin description pin symbol no. type name and function drcom 1 p digital output driver ground. bit 12 2 do data bit (lsb). bit 2C11 3C12 do data bits. bit 1 13 do data bit (msb). drv dd 14 p +5 v digital output driver sup- ply. otr 15 do out of range is active high on the leading edge of code 0 or the trailing edge of code 4096. see output data format table v. clock 16 di sample clock. v dd 17 p +5 v digital supply. dcom 18 p digital ground. refcom 19, 24 p analog ground. refout 20 ao 2.5 v reference output (decouple with 1 m f ceramic capacitor to refcom). ain1 21 ai analog input. ain2 22 ai analog input. refin 23 ai reference input. ncomp2 25 ao noise compensation (decouple with 1 m f ceramic capacitor to acom). ncomp1 26 ao noise compensation (decouple with 1 m f ceramic capacitor to acom). acom 27 p analog ground. v cc 28 p +5 v analog supply. type: ai = analog input; di = digital input; p = power; ao = analog output; do = digital output. ordering guide model temperature range package ad1672ap C40 c to +85 c p-28a pin configuration 7 8 9 10 11 5 6 28 27 26 1 2 3 4 21 22 23 24 25 19 20 12 13 14 15 16 17 18 top view (not to scale) pin 1 identifier bit 9 bit 8 bit 7 bit 6 bit 5 ncomp2 refcom refin ain2 ain1 ad1672 bit 4 bit 3 refout refcom acom bit 10 bit 11 bit 12 (lsb) drcom v cc (msb) bit 1 ncomp1 bit 2 drv dd otr clock v dd dcom obsolete
ad1672 rev. 0 C6C definitions of specifications integral nonlinearity error (inl) integral nonlinearity error refers to the deviation of each individual code from a line drawn from negative full scale thr ough positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition (all zeros to only the lsb on). positive full scale is defined as a level 1 1/2 lsb beyond the last code transition (to all ones). the deviation is measured from the middle of each particular code to the true straight line. differential linearity error (dnl, no missing codes) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus every code must have a finite width. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges. unipolar offset error in the unipolar mode, the first transition should occur at a level 1/2 lsb above analog common. unipolar offset is defines as the deviation of the actual from that point. bipolar zero error in the bipolar mode, the major carry transition should occur for an analog value 1/2 lsb below analog common. zero error is defined as the deviation of the actual transition from that point. gain error the first transition should occur for an analog value 1/2 lsb above nominal negative full scale. the last transition should occur for an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. power supply rejection one of the effects of power supply error on the performance of the device will be a small change in gain. the specifications show the maximum change in the converters full scale as the supplies are varied from minimum to maximum values. aperture jitter aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the a/d. code transition noise the effects of noise are to introduce an uncertainty in the pre- cise determination of the analog input values at which the out- put code transitions take place, and, in effect, to increase or reduce the quantization band. code transition noise describes the quantization band variation resulting from noise in terms of rms lsbs. aperture delay aperture delay is a measure of the sample-and-hold (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. overvoltage recovery time overvoltage recovery time is defined as that amount of time required for the adc to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converters range. dynamic specifications signal-to-noise and distortion (s/n+d) ratio s/n+d is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. intermodulation distortion (imd) with inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. . . . intermodulation terms are those for which m or n is not equal to zero. for example, the second order terms are (fa + fb) and (fa C fb) and the third order terms are (2 fa + fb), (2 fa C fb), (fa + 2fb) and (2 fb C fa). the imd products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distor- tion terms. the two signals are of equal amplitude and the peak value of their sums is C0.5 db from full-scale. the imd prod- ucts are normalized to a 0 db input signal. full-power bandwidth the full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 db for a full-scale input. spurious free dynamic range the difference, in db, between the rms amplitude of the input signal and the peak spurious signal. obsolete
ad1672 rev. 0 C7C sample rate: 3 msps and ain = C0.5 db code 1.0 ?.0 0 4000 500 dnl error ?lsb 1000 1500 2000 2500 3000 3500 0.8 0.2 ?.2 ?.6 -0.8 0.6 0.4 0.0 ?.4 figure 2. typical dnl performance input frequency ?hz s/(n+d) db 80 40 10 5 10 7 10 6 75 70 ?.5db ?6.0db 60 55 50 45 65 ?20.0db figure 3. s/(n+d) vs. input frequency inl error ?lsb code 2.5 ?.5 0 4000 500 1000 1500 2000 2500 3000 3500 2.0 0.5 ?.5 ?.5 ?.0 1.5 1.0 0.0 ?.0 figure 4. typical inl performance amplitude ?db 70 58 ?0 0 ? 68 60 ? 62 64 66 s/(n+d) db ? ? ? ? ? ? ? 500khz 1.5mhz 1mhz figure 5. s/(n+d) vs. amplitude input frequency ?hz amplitude ?db ?0 ?0 ?0 10 5 10 7 10 6 ?0 ?0 ?0 thd 2nd harm 3rd harm figure 6. distortion vs. input frequency, full-scale input typical performance characteristicsCad1672 rev. 0 C7C obsolete
sample rate: 3 msps and ain = C0.5 db 15db/div 1 3 4 5 78 9 6 2 thd = ?4.42db s/(n+d) = 68.83db sfdr = ?8.79db harmonics ?db 2nd ?9 6th ?6 3rd ?6 7th ?3 4th ?8 8th ?5 5th ?1 9th ?6 figure 7. typical fft, f in = 525 khz ad1672Cdynamic characteristics rev. 0 C8C 15db/div 1 3 4 5 7 8 9 6 thd = 60.12db s/(n+d) = 59.70db sfdr = 61.09db harmonics ?db 2nd ?1 6th ?9 3rd ?7 7th ?1 4th ?8 8th ?3 5th ?8 9th ?7 2 figure 8. typical fft, f in = 1.450 mhz theory of operation the ad1672 is implemented using a 4-stage pipelined multiple flash architecture. the flash resolution for the stages is 4-4-3-4 with one-bit of overlap used between stages for error correction. a low noise sample-and-hold amplifier (sha) acquires a full- scale, single-ended input to 12-bit accuracy within 167 ns. a 4-bit approximation of the input is made by the first flash con- verter, and an accurate analog representation of this four-bit es- timate is generated by a digital-to-analog (dac) converter. this approximation is subtracted from the sha output to pro- duce a remainder, or residue. this residue is then sampled and held by the second sha, and a 4-bit approximation is generated and subtracted by the second stage. once the second sha goes into hold, the first stage goes back into sample mode to acquire a new input signal. the third stage which has 3 bits of resolution is similar to the first and second stage in that each stage consists of a sha, flash adc, and a dac. each stage preforms a 4- (or 3-) bit ap- proximation/subtraction operation with the residue of each stage being passed on to the next stage. the fourth or last stage con- sists only of a 4-bit flash adc which converts the final residue. the 15 output bits from the 4 flash converters are accumulated in the correction logic block, which adds the bits together using the appropriate correction algorithm, to produce the 12 bit output word. the digital output, together with the overrange indicator (otr), is latched into an output buffer to drive the output pins. the additional sha inserted in each stage of the ad1672 archi- tecture allows pipelining of the conversion. in essence, the con- verter is converting multiple inputs simultaneously, processing them through the converter chain serially. this means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes 2 1/2 clock cycles for the con- version to be fully processed and appear at the output. this pipeline delay is often referred to as latency, and is not a con- cern in most applications, however there are some cases where it may be a consideration. for example, some applications call for the a/d converter to be placed in a high speed feedback loop, where its input is servoed to provide a desired result at the digi- tal output (e.g., offset calibration or zero restoration in video applications). in these cases the clock cycle delay through the pipeline must be accounted for in the loop stability calculations. also, because the converter is working on three conversions si- multaneously major disruptions to the part (such as a large glitch on the supplies or reference) may corrupt three data samples. finally, there will be a minimum clock rate below which the sha droop corrupts the signal in the pipeline. in the case of the ad1672, this minimum clock rate is 20 khz at 25 c. the ad1672 clock circuitry uses both edges of the clock in its internal timing circuitry (see specification page for exact timing requirements). the ad1672 samples the analog input on the rising edge of the clock input. during the clock low time (be- tween the falling edge and rising edge of the clock), the input sha is in sample mode; during the clock high time it is in hold. system disturbances just prior to the rising edge of the clock may cause the part to acquire the wrong value, and should be minimized. while the part uses both clock edges for its timing, jitter is only a significant issue for the rising edge of the clock (see clock input section). obsolete
ad1672 rev. 0 C9C applying the ad1672 analog inputs figure 9 shows the equivalent analog input of the ad1672. the input sha and associated resistor network topology can be eas- ily configured for either unipolar (0 v to 2.5 v, 0 v to 5.0 v) or bipolar (C2.5 v to 2.5 v) input signals as shown in figure 10. the nominal input resistance, r in , of the ad1672 is 2 k w for a 2.5 v span and 4 k w for a 5 v span. the circuit topology both level shifts and inverts the analog input for the various input spans. sha out ain 1 4k w 2k w v bias 1.25v 4k w ain 2 2k w figure 9. equivalent analog input circuit 21 22 20 23 1? ain1 ain2 refout refin ad1672 v in 21 22 20 23 1? ain1 ain2 refout refin ad1672 v in 21 22 20 23 1? ain1 ain2 refout refin ad1672 v in a. 0 to +2.5 v input range b. 0 to +5.0 v input range c. ?.5 to +2.5 v input range figure 10. input range connections in applications where ac coupling of the analog input signal is appropriate such as in a single supply system, the user can capacitively couple the input signal for a 2.5 v or 5 v span thus removing any preceding system dc offsets. figure 11 shows the proper configurations of the ad1672 for ac coupling. main- taining the specifications outlined in the data sheet requires care- ful selection of the component values. the most important concern is that the f C3 db high pass corner is a function of c1 and c2 in parallel with r in . the f -3 db point can be approximated by the equation / f 3 db = 1/(2 p r in c eq ) where c eq is the parallel combination of c1 and c2. note that c1 is typically a large electrolytic or tantalum capacitor that be- comes inductive at high frequencies. adding a small ceramic capacitor on the order of 0.1 m f that does not become inductive until negligibly higher frequencies maintains a low impedance over a wide frequency range. 21 22 25 20 23 c1 10? c2 1.0? 10? 1.0? analog input ain1 ain2 ncomp2 ref out refin ad1672 21 22 25 20 23 c1 10? c2 1.0? 10? 1.0? analog input ain1 ain2 ncomp2 ref out refin ad1672 2.5v span 5.0v span figure 11. ac coupled inputs in applications requiring dc coupling, a buffer amplifier is rec- ommended for driving the ad1672 input. any source resis- tance will contribute to both gain and offset error due to its interaction with the ad1672s input resistance. the particular application and signal input range will determine how the buffer amplifier is configured. for example, in dc precision applica- tions, the buffer amplifier can be configured for convenient gain and offset adjustment as shown in figure 12. in spectral analysis/signal processing applications, the buffer amplifier can be configured as a 2nd order antialiasing filter in a sallen-key or multiple-feedback topology as shown in figure 13. v cc 500 w 50 w 500 w 5k w 50 w 5k w 0.1? v ee analog input offset adjustments gain adjustment ad1672 ain figure 12. offset and gain adjustment v in v out c2 r4 c1 r2 r1 r3 v in v out c2 c1 r2 r1 r3 figure 13. sallen-key and multiple-feedback antialiasing filter topologies in imaging and multiplexed data acquisition applications, the ad1672s wide input bandwidth facilitates rapid acquisition of transient input signals: the input sha can typically settle to 12- bit accuracy from a full scale input step in less than 150 ns. fig- ure 14 illustrates the typical acquisition of a full scale input step. for amplifiers that are powered by supplies greater than 6.5 v, it is recommended that a clamping circuit be included at the input of ad1672. this circuit limits the input voltage to 6.5 v under a fault condition. obsolete
ad1672 rev. 0 C10C the selection of the buffer is of particular concern in preserving the performance of the ad1672. the total output referred- noise contribution of the selected amplifier should be less than 200 m v rms to preserve the ad1672s noise performance. the amplifiers harmonic distortion should be 12 db or better in per- formance than the ad1672 over the bandwidth and signal level range of the particular application. the selected amplifier should settle to 0.01% within 70 ns. table i lists the performance of various suitable amplifiers when configured for a gain of +1 or C1 with the ad1672 configured for 2.5 v bipolar operation and f clock = 3 mhz. the ad80xx family of high speed amplifiers are only suitable for 2.5 v bipolar and 0 vC2.5 v unipolar operation due to their power- supply range and voltage output swing constraints. note that the snr, thd, and sfdr results in tables i, ii and iii are for a 750 khz full-scale (C0.5 db) input signal. these results were determined experimentally using the ad1672 evaluation board, and hence the stated amplifiers performance is inclusive of the ad1672. table i. C2.5 v to +2.5 v range adi part # snr thd sfdr gain ad8047 70.5 C67.5 C68.4 +1 ad8041 70.0 C67.3 C68.2 +1 ad8011 70.5 C67.0 C67.8 +1 ad817 70.4 C62.1 C62.9 +1 ad818 70.3 C65.0 C68.0 C1 ad811 70.3 C61.9 C63.4 +1 w/o op amp 70.5 C67.5 C68.4 table ii lists the performance of three high speed amplifiers which are configured for a gain of +1 or C1 with the ad1672 confi gured for 0 v to 5 v unipolar operation and f clock = 3 mhz. note that these amplifiers may operate at the higher power sup- ply range to achieve the 0 v to 5 v output swing. table ii. 0 v to +5 v range settling adi time (ns) part # snr thd to 0.01% gain ad811 70.1 C67.6 65 +1 ad817 70.1 C68.9 70 +1 ad818 70.0 C67.4 80 C1 table iii lists the performance of two high speed amplifiers specified for single supply operation. they are configured for a gain of +1 with the ad1672 configured for 0 v to 2.5 v unipolar operation and f clock = 3 mhz. the output of these amplifiers are ac coupled to the ad1672. table iii. ac coupled 0 v to 2.5 v range adi part # snr thd sfdr ad8011 70.1 C70.0 C71.6 ad8041 69.7 C71.3 C73.4 nsec 0 160 20 40 60 80 100 120 140 4500 4000 0 2000 1500 1000 500 3000 2500 3500 code out figure 14. typical ad1672 settling time the ad1672 will contribute its own wideband thermal noise. as a result of the integrated wideband noise (1/4 lsb rms, referred-to-input), applying a dc analog input produces more than one code at the output. a histogram analysis of the ad1672 with a dc input is shown in figure 15. it shows a bell shaped curve consistent with the gaussian nature of the thermal noise. this histogram will be approximately 3 codes wide, depending on how well the input is centered on a given code and how many samples are taken. figure 16 illustrates the ad1672s transition noise. deviation from correct code ?lsb 2100000 1800000 0 1200000 900000 600000 300000 1500000 +1 ? 0 # code hits 2015807 13639 67324 figure 15. typical grounded histogram 100 90 0 60 30 20 10 80 70 40 50 100 x p ( 3 code x + 1) s = 0.25 lsb rms code x code x ? 1 figure 16. code probability at a transition obsolete
ad1672 rev. 0 C11C reference input the nominal reference input is 2.5 v, taken with respect to refcom. the reference input pin (refin) can be connected to the reference output pin (refout) or a standard external +2.5 volt reference can be selected to meet specific system re- quirements. figure 17 shows the ad1672s refin being driven from an external precision voltage reference such as the ref192. if an external reference is used, refout can be ef- fectively disabled by tying it directly to the positive supply volt- age v cc . note that if the reference is changed during a conversion, all three conversions in the pipeline will be invalidated . the nominal 2.5 v reference input is rescaled to 1.25 v via a resistor divider network as shown in figure 18. the nominal resistance of this resistor network is 8 k w . table iv summa- rizes various 2.5 v references for use with the ad1672 (see reference output section). table iv. suitable 2.5 volt references drift initial accuracy (ppm/ 8 c) % ref43b 10 (max) 0.1 ref192e 5 (max) 0.08 ad780b 3 (max) 0.04 0.1? 10? +v cc +v cc ad780 output gnd v s 1? ad1672 refin refout figure 17. circuit using ad780 optional +2.5 v reference input circuit reference noise reduction figure 18 shows the proper connection of two external 1 m f capacitors, c nr1 and c nr2 , associated with the two noise re- duction nodes ncomp1 and ncomp2 (pins 25 and 26) of the ad1672. although these noise reduction capacitors, cnr, are not required for stability, the most optimum noise and distortion per- formance will be attained with a 1 m f ceramic capacitor connected from each noise reduction node to acom . c nr1 is associated with the output of the dac amp and is required for optimum dis- tortion performance and sha settling time. it provides a low source impedance for signal-dependent, transient currents asso- ciated with this node. c nr2 reduces the noise contribution from the reference buffer amplifier. cnr2 1? 1? cnr1 1? ncomp2 refout refin ad1672 refcom ncomp1 dac amp ref amp 4k w 4k w 20 23 24 25 26 figure 18. reference noise reduction reference output the ad1672 includes an onboard +2.5 v curvature compen- sated bandgap reference that has been laser trimmed for both absolute value and temperature drift. the reference must be externally compensated with a capacitor of 1 m f or greater from refout to refcom. the reference is specified to provide an additional load current up to 500 m a. for large dynamic loads and/or external loads greater than 500 m a, an external buffer amplifier or pull-up re- sistor is required. if a pull-up resistor is used, its value should be selected such that refout will not be required to sink any current under all operating conditions. figure 19 illustrates the load regulation of the reference. the power supply rejection of the reference is better than 0.2 % of fsr at dc. load current ?? reference voltage ?volts 2.500 2.493 2.490 0 100 200 300 400 500 600 700 800 900 1000 2.499 2.494 2.492 2.491 2.498 2.496 2.497 2.495 figure 19. reference output voltage vs. load current digital outputs the ad1672 output data is presented in positive true straight binary for both the 0 v to 2.5 v and 0 v to 5 v unipolar input ranges and positive true offset binary for the 2.5 v bipolar range. table v indicates the output data formats for the three analog input ranges. users requiring twos complement encoding for the 2.5 v range may simply invert the msb (pin 13). table v. output data format input voltage range +fs (v) Cfs (v) lsb (mv) 0 to +2.5 +2.5 0.0 0.610 0 to +5.0 +5.0 0.0 1.22 C2.5 to +2.5 +2.5 C2.5 1.22 ?s+1/2 lsb ?s ?s ?/2 lsb +fs +fs ?/2 lsb otr +fs ? 1/2 lsb otr data outputs 1 1111 111 1111 0 1111 1111 1111 0 1111 1111 1110 0 0000 0000 0001 0 0000 0000 0000 1 0000 0000 0000 figure 20. output data format obsolete
ad1672 rev. 0 C12C the ad1672s cmos digital output drivers can be configured to interface with +5 v or +3.3 v logic families by setting drv dd to +5 v or +3.3 v respectively . they are also sized to provide sufficient output current to drive a wide variety of logic families. however, large drive currents tend to cause glitches on the supplies and may effect s/(n+d) performance. applica- tions requiring the ad1672 to drive large capacitive loads or large fanout may require additional decoupling capacitors on drv dd and dvdd. in extreme cases, external buffers or latches may be required. out of range an out-of-range condition exists when the analog input voltage is beyond the input range (0 v to +2.5 v, 0 v to +5.0 v, 2.5 v) of the converter. otr (pin 15) is a digital output which is up- dated along with the data output pertaining to the particular sampled analog input voltage. hence, otr has the same pipe- line delay (latency) as the digital data. it is set low when the analog input voltage is within the analog input range. it is set high and will remain high when the analog input voltage exceeds the input range by typically 1/2 lsb from the center of the full-scale output codes. otr will remain high until the analog input is within the input range and another conversion is completed. by logical anding otr with the msb and its complement, overrange high or underrange low conditions can be detected. table iv is a truth table for the over/under range circuit in figure 20 which uses nand gates. systems requir- ing programmable gain conditioning prior to the ad1672 can immediately detect an out-of-range condition, thus eliminating gain selection iterations. also, otr can be used for digital off- set and gain calibration (see gain and offset adjustment). table vi. out-of-range truth table otr msb analog input is 0 0 in range 0 1 in range 1 0 underrange 1 1 overrange over = ? under = ? msb otr lsb figure 21. overrange or underrange logic clock input the ad1672 internal timing control uses the two edges of the clock input to generate a variety of internal timing signals. the clock input must meet or exceed the minimum specified pulse width high and low (t ch and t cl ) specifications of 167 ns to maintain the ad1672s rated performance. at a clock rate of 3 msps, the clock input must have a 50% duty cycle to meet this timing requirement. for clock rates below 3 msps, the duty cycle may deviate from 50% to the extent that both tch and tcl are satisfied. one way to minimize the tolerance of a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in figure 22. 6mhz clk 3mhz +5v r q q d s +5v figure 22. divide-by-two clock circuit in this case, a 6 mhz clock is divided by 2 to produce the 3 mhz clock input for the ad1672. in this configuration, the duty cycle of the 6 mhz clock is irrelevant. the input circuitry for the clock pin is designed to accom- modate cmos inputs. the quality of the logic input, particu- larly the rising edge, is critical in realizing the best possible jitter performance for the part: the faster the rising edge, the better the jitter performance. the offset of the ad1672 is sensitive to the rising edge (i.e., dv/dt) seen at clock due to clock feedthrough. an addi- tional offset component becomes noticeable for rise times below 10 ns and causes an additional few lsbs of offset. the amount of additional offset is dependent on dv/dt of the rising edge and hence will remain constant for nonvarying rising edges. for applications which are sensitive to a change in offset due to a variation in the rise edge, the clock rise time may be reduced by selecting a slower logic family or installing a 1 k w resistor be- tween the clock driver and clock of the ad1672. as a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. jitter-induced errors become more predomi- nant at higher frequency, large amplitude inputs, where the input slew rate is greatest. although the ad1672 is designed to support a sampling rate of 3 msps, operating at slightly faster or slower clock rates may be possible with a minimum degradation in performance levels. fig- ure 23 is a plot of the s/(n+d) vs. clock frequency for a 500 khz analog i nput. in fact, the ad1672 is capable of operating with a clock frequency as low as 20 khz frequency ?mhz 75 70 50 05 0.5 s/(n+d) db 1 1.5 2 2.5 3 3.5 4 4.5 65 60 55 figure 23. typical s/(n+d) vs. clock frequency; f in = 500 khz, full-scale input obsolete
ad1672 rev. 0 C13C the power dissipated by the correction logic and output buffers is largely proportional to the clock frequency; runn ing at reduced clock rates provides a slight reduction in power consumption. figure 24 illustrates this tradeoff. frequency ?mhz 260 252 244 250 248 246 258 256 254 05 0.5 power ?mw 1 1.5 2 2.5 3 3.5 4 4.5 figure 24. typical power dissipation vs. clock frequency grounding and power supply decoupling rules proper grounding and decoupling should be a primary design objective in any high speed, high resol ution system. the ad1672 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, v cc , the analog supply, should be de- coupled to acom, the analog common, as close to the chip as physically possible. similarly, v dd , the digital supply, should be decoupled to dcom as close to the chip as physically as pos- sible. drv dd , the digital supply for the output drivers should be decoupled to drcom which is also connected to the digital ground plane. figure 31, the ad1672/eb evaluation board schematic, demon- strates the recommended decoupling strategy for the supply pins. note that in extremely noisy environments, a more elabo- rate supply filtering scheme may be necessary. figure 25 shows the power supply rejection ratio vs. frequency for 100 mv of frequency ?mhz 110 0.2 supply rejection ?db 2 ?0 ?20 ?0 ?0 ?0 ?0 v cc v dd drv dd ?0 ?0 ?00 ?10 0.1 0.5 5 figure 25. power supply rejection vs. frequency, 100 mv p-p signal on power supplies frequency ?mhz 0.1 10 0.2 2 75 65 60 55 40 50 45 70 drv dd v cc v dd 5 1 0.5 s/(n+d) ?db figure 26. s/(n+d) vs. supply noise frequency power supply ripple at various frequencies. figure 26 shows the degradation in s/(n+d) ratio resulting from this 100 mv power supply ripple for a full-scale analog input at 500 khz. the ad1672/eb evaluation board was used to generate these graphs the ad1672 is designed to minimize the code dependent cur- rent at refcom, therefore reducing input dependent analog ground voltage drops and errors. the majority of code depen- dent ground current is diverted to acom. the digital activity on the ad1672 chip falls into two general categories: cmos correction logic, and cmos output drivers. the internal correction logic draws relatively small surges of current which flow through v dd and dcom. the output drivers draw large current impulses while the output bits are changing. the size and duration of these currents is a function of the load on the output bits: large capacitive loads are to be avoided. the output drivers are supplied through drv dd and drcom. a 0.1 m f ceramic capacitor for decoupling the driver supply, drv dd , is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pf on each pin). applica- tions involving greater digital loads should consider increasing the digital decoupling proportionately. for those applications that require a single +5 v supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in figure 27. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained using low esr (equivalent series resistance) type electrolytic and tantalum capacitors. ferrite beads 100? elect. 10?0? tant. 0.1? cer. +5v agnd +5v dgnd +5v power supply ttl/cmos logic circuits figure 27. di fferential lc filter for single +5 v applications obsolete
ad1672 rev. 0 C14C gain and offset adjustment the ad1672 is factory trimmed to minimize gain, offset and linearity errors. in some applications, the gain and offset errors need to be externally trimmed to zero. since the gain and offset errors of the ad1672 are interdependent, an iterative process is required to trim both errors. the otr pin can be monitored to trim the offset and gain errors to within 1/2 lsb of negative and positive full-scale (i.e., Cfs and +fs) respectively. in this case, the calibration procedure would be to iterate between Cfs and +fs voltage levels which are applied to the input of the ad1672 and adjust the offset and gain until otr toggles at both Cfs and +fs. both gain and offset errors may be trimmed with external cali- bration circuits based on a potentiometer or a dac. digital calibration circuits using a dac offers greater flexibility and can be programmed for various operating conditions. the fol- lowing digital calibration circuits are based on the dac08 which is a low cost, 8-bit current output dac with 85 ns set- tling time performance. different adjustment spans and resolu- tion may be achieved by judicious selection of the resistors in the circuit. figure 28 shows an offset correction circuit for the unipolar input ranges of 0 v to 2.5 v and 0 v to 5.0 v. the complemen- tary current outputs of the dac08 provide a bipolar adjustment range at the output of the op amp if r s is made equal to r f /g. g is the noninverting gain of the op amp and is equal to 1 + r f /r a . refout divided by r in sets the full-scale current output, i fs , for the dac08 note, r p is a pull-up resistor used to source additional current if i fs is greater than 500 m a. the bipolar voltage adjustment span at the output of the op amp is equal to i fs r f . r i isolates the op amp from the dac08 output capacitance. note, that the values of these resistors can be optimized for any circuit requirement or adjustment span since they are not uniquely defined for any given voltage span. r f r a r i r i v ref(+) v ref(? dac08 i o i o r in r in 1? r p ad1672 ain refout +v cc figure 28. unipolar offset correction using the dac08 figure 29 shows an offset correction circuit for the bipolar input range of C2.5 to +2.5 v. this circuit is similar to the circuit shown in figure 28 except that the op amp is configured in an inverting topology so that the voltage compliance of the dac08 is not exceeded. r f r a r i r i v ref(+) v ref(? dac08 i o i o r in r in 1? r p +v cc r s ad1672 ain refout figure 29. bipolar offset correction using the dac08 figure 30 shows a gain correction circuit which is also similar to the circuit shown in figure 28. the circuit consists of a unity gain amplifier in which r s and r f are equal to 158 w . in this case, the full-scale output current of the dac08, i fs , is set at 500 m a to minimize the load to the ad1672 refout. the output of the op amp can be varied over a 78 mv range around the midscale voltage of refout. also, r s and r f are selected such that 1 lsb of the dac08 corresponds to 1 lsb of the ad1672. 500 w 5k w 5k w 1? 4.7k w +v cc ad1672 refin refout 2.5v v ref(+) v ref(? dac08 i o i o 500 w 158 w 158 w 2.5 0.078v figure 30. gain correction using the dac08 output latches the ad1672/eb evaluation board schematic in figure 31 shows the ad1672 connected to the 74hc541 octal/buffer line drivers with three-state outputs. the latch can drive highly ca- pacitive loads (i.e., bus lines, i/o ports) while maintaining the data signal integrity. ad1672 evaluation board general description the ad16 72/eb is an evaluation board for the ad1672 12-bit 3 msps analog-to-digital converter (adc). figure 31 shows the schematic for the ad1672/eb evaluation board. careful attention to layout and circuit design combined with analog and digital proto- typing areas allows the user to easily and effectively evaluate the ad1672 in any application requiring high resolution, high speed conversion. the analog input to the ad1672/eb may be driven directly or via an onboard buffer amplifier. the ad1672/eb contains an 8-bit dac which can be easily configured for input offset ad- justment or for reconstruction of the digital output. an optional external voltage reference is included for greater dc precision obsolete
ad1672 rev. 0 C15C and/or offset adjustment purposes. onboard data buffers are also included. the ad1672/eb requires an external clock which is applied from a users bench or generated from a circuit built on the prototyping area. a standard 40-pin idc-connector provides access for the digital outputs from the ad1672/eb. the user must also provide a digital +5 v power supply and analog 5 v supplies to operate the ad1672/eb. operating procedure and functional description power apply power to the ad1672/eb by attaching banana plugs to the appropriate banana jacks on the printed circuit board (fig- ure 31). the +v cc analog supply should be +5 v ( 5%) and be capable of supplying 70 ma. the Cv ee analog supply should be C5 v ( 5%) and be capable of supplying 20 ma. the +v dd digital supply should be +5 v ( 5%) and be capable of supply- ing 12 ma (not including any additional current required by the digital load). the power supply pin for the onboard output drivers internal to the ad1672 (drv dd Cpin 14) can be driven directly by the digital supply, +v dd , by installing jp10 or may be driven via a separate supply by removing jp10 and driving the test point, tp5. the separate supply option allows the user to interface with +5 v or +3.3 v ( 5%) logic families. jp1 to provide +v cc supply to both u3 (dac08) and u1 (op amp), attach jumper jp1. jp10 to provide +5 v (+/-5%) supply to drv dd pin of ad1672 via +v dd or separate supply. to provide power to drv dd pin via +v dd , install jp10. to provide power to drv dd pin via separate supply, remove jp10 and con- nect external supply to test point tp5. analog inputs the bnc jack, ain (j1), accepts voltage inputs that comply with the analog input requirements of the ad1672. it is termi- nated with a 49.9 w resistor (r1) located on the component- side of the evaluation board. remove and/or replace this resistor with other values in order to match different cable im- pedances. the ad1672 analog input can be directly driven via ain (j1) by installing jp2 and removing jp3 or it can be driven via an amplifier (u1) by installing jp3 and removing jp2. the amplifier (u1) may be configured in the inverting or noninvert- ing mode with a gain of one by configuring s4. jp2 installing jp2 and removing jp3, directly dc couples ain (j1) to the ad1672 analog input. jp3 installing jp3 and removing jp2, indirectly dc couples ain (j1) to the ad1672 analog input via the inverting op amp u1. s4 selects inverting or noninverting gain of one for the am- plifier u1. when s4 is in position a, the noninverting mode is selected. when s1 is in position b, the inverting mode is selected. the ad1672s analog input range can be conf igured for 0 vC2.5 v, 0 vC5 v, or 2.5 v by installing only one of the four jumpers, jp5Cjp7, as outline in table vii. jp5 installing only jumper jp5, the 0 vC2.5 v range of the ad1672 is selected. jp6 installing only jumper jp6, the 0 vC5 v range of the ad1672 is selected. jp7 installing only jumper jp7, the 2.5 v range of the ad1672 is selected. table vii. analog input range selection analog input range (volts) jp5 jp6 jp7 0 to 2.5 on off off 0 to 5.0 off on off 2.5 off off on reference an external 2.5 v voltage reference, u2, is also included on the ad1672/eb to provide the option for greater dc precision than the ad1672s internal reference. the external reference also provides the proper biasing currents for the offset adjustment circuitry consisting of u3. to use the external voltage reference for the ad1672, install jp9 and remove jp4. to use the ad1672s internal voltage reference, install jp4 and remove jp9. jp4 installing jp4 and removing jp9 selects the ad1672s internal reference. jp9 installing jp9 and removing jp4 selects the external reference, u2. offset adjustment/reconstruction dac an 8-bit complementary current output dac08, u3, allows for either offset adjustment of the analog input or reconstruction of the ad1672 digital output for simple evaluation purposes. the offset adjustment option is implemented by installing both jp3 and jp8. note that jp5, jp6 and jp7 should be removed so that the ad1672 is configured for a 0 vC5 v range. the dac08 can also be configured to reconstruct the digital output of the ad1672 using its digital output for the dac08s digital input. the output of the user supplied ribbon cable used to interface with the 40-pin idc connector (e1) can be con- nected directly to the connector u8, hence recirculating the eight most significant digital output bits of the ad1672. in this configuration, jp8 would be removed and the reconstructed waveform ( 50 mv p-p) can be monitored via test point tp4. jp8 installing jp8 and removing jp5, jp6 and jp7 selects the offset adjustment option. removing jp8 and connecting e1 to u8 via an external user-supplied ribbon cable selects the reconstruction option. obsolete
ad1672 rev. 0 C16C clock input a 49.9 w resistor (r9) terminates this input. remove and/or replace this resistor with other values in order to match different cable impedances. an external sample clock must be provided to the bnc connector labeled clk (j5). the rising or falling edge of clk can be selected to trigger a conversion and is avail- able to the user via the connector e1 by configuring s1 and s3. the clk input has two modes of operation which is determined by the position of s5. when s5 is in position b, the clk is directly coupled to u5, a hex inverter with schmitt trig- ger inputs. the requisite input levels are cmos-compatible in this mode. when s5 is in position a, the clk is ac coupled via c23 and level shifted via r10, r12, and r13. this mode is used to generate a low jitter clock input for the ad1672 with a tunable duty cycle. the input to clk (j5) is a filtered 5 v p-p sine wave at the desired sampling frequency. the duty cycle may be adjusted via r10. s1 selects the rising or falling edge of clk to initiate a con- version. when s1 is in position a, the falling edge of clk is selected. when s1 is in position b, the rising edge of clk is selected. s3 selects the rising or falling edge of clk made available to the user via the connector via e1, pin 33. when s3 is in position a, the rising edge of clk is selected. when s1 is in position b, the falling edge of clk is selected. s5 selects clk input mode of operation. if s5 is in posi- tion a, the low jitter, ac coupled mode of operation is se- lected. if s5 is position b, the dc coupled mode of operation is selected. digital inputs/outputs the digital outputs of the ad1672 are buffered and connected to a 40-pin idc connector (e1). the digital output can be ei- ther in a straight binary or twos complement format by configur- ing s2. s2 selects the msb output or its complement. the out-of-range (otr) output is available on test point, otr. s2 selects either the msb or its complement for either straight binary or twos complement digital output data formatting, respectively. when s2 is in position a, the straight binary format is selected. when s2 is in position b, the twos complement format is selected. layout considerations figure 31 to 34 show the schematic diagram, component layout, trace routing, and silk screening for the ad1672 4-layer evaluation board. figure 35 and 36 show the ad1672 ground and power plane layouts. the ad1672-eb is a 4-layer evaluation board consisting of separate ground and power plane layouts. separate ground and power planes have several advantages for high speed layouts. (for further information outlining these advantages, see the application note design and layout of a video graphics sys- tem for reduced emi [e1309] available from analog devices [(617) 461-3392].) the ground planes are separated into ana- log and digital planes that are joined together under the ad1672. the ad1672 should be treated as an analog component and a common ground connection should be made underneath the ad1672 despite some pins being labeled digital and some as analog ground plane. a summary of the test point designators and a parts list is given in table viii and ix. table viii. summary of test point designators test point description tp1 agnd tp2 ain tp3 v cc for u1 and u3 tp4 dac08 (u3) v out tp5 drv dd tp6 dgnd tp7 clk table ix. ad1672 eb parts list reference value/part type package qty/bd u1 ad8047 8-pin dip 1 u2 ref192 8-pin dip 1 u3 dac08 16-pin dip 1 u4 ad1672 28-pin plcc 1 u5 74hc14n 14-pin dip 1 u6, u7 74hc541n 20-pin dip 2 ain, clk bnc jacks small, vertical 2 jp1C10 headers/shunts 2-pin 10 s1-s5 spdt, secme 0.1" 0.3" 5 e1 40-pin idc r.a., male 1 connector w/latches r1, r9 50 w 1%, 1/4 w 2 r2Cr4 499 w 1%, 1/4 w 6 r11Cr13 r5 4.99 k w 1%, 1/4 w 1 r6 100 w 1%, 1/4 w 1 r7, r8 2.49 k w 1%, 1/4 w 2 r10 2.0 k w pot 1%, 1/4 w 2 c1, c2, c4, 0.1 m f ceramic, smt 11 c12Cc16, c18Cc20 c3, c6Cc9, 1.0 m f ceramic, 8 c11, c22, c23 throughhole c5, c17, c21 10 m f tantanlum 3 throughhole c10 0.01 m f ceramic 1 c24 47 m f alum. elect. 1 obsolete
ad1672 rev. 0 C17C s3 a b 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 36 38 40 34 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 a tp9 agnd agnd a tp12 +v dd c21 10? 16v tp11 dgnd dgnd +v dd a tp10 +v cc c17 10? 16v +v cc tp8 ? ee c5 10? 16v ? ee c1 1? j3 j7 j6 j4 j2 5 6 7 8 9 10 11 12 13 2 a a c15 0.1? 1 3 5 7 9 11 13 15 u8 u8 u8 u8 u8 u8 u8 u8 2 4 6 8 10 12 14 16 u8 u8 u8 u8 u8 u8 u8 u8 a r7 2.5k w 15 a 16 1 4 c10 0.1? a1 a2 a3 a4 a5 a6 a7 a8 v cc gnd v ref(? comp nc io dac08 u3 v ref(+) ? ee c16 0.1? 14 r8 2.5k w r6 100 w r5 5k w tp4 a ref192 4 6 2 +v cc c4 0.1? s5 a b 9 8 u5 74hc14 c18 0.1? +v dd 11 10 u5 74hc14 13 12 u5 74hc14 v in v out gnd u2 a c22 1? 3 2 4 7 6 u1 ad8047 a r4 500 w a s4 a b eref jp9 a c2 0.1? ? ee r3 500 w tp2 r1 50 w a ain tp1 j1 jp1 +v cc a c1 0.1? tp3 r2 500 w jp3 jp2 a c8 1? jp4 a a c6 1? jp5 jp7 jp8 jp6 a 3 v ee a a c7 1? +v dd c11 1? c12 0.1? +v cc c9 1? c14 0.1? a s2 a b 3 4 u5 74hc14 jp10 tp5 c13 0.1? +v dd otr 18 17 16 15 14 13 12 11 20 74hc541n c19 0.1? +v dd 1 19 2 3 4 5 6 7 8 10 9 g1 g2 a0 a1 a2 a3 a4 a5 a6 a7 gnd y0 y1 y2 y3 y4 y5 y6 y7 +5vd u6 tp7 r9 50 w clk j5 cw c23 1? r10 2k w r13 500 w 18 17 16 15 14 13 12 11 20 74hc541n c20 0.1? +v dd 1 19 2 3 4 5 6 7 8 10 9 g1 g2 a0 a1 a2 a3 a4 a5 a6 a7 gnd y0 y1 y2 y3 y4 y5 y6 y7 +5vd u7 s1 a b 5 6 u5 74hc14 c24 47? r12 500 w +v dd 1 2 u5 74hc14 r11 500 w 3 25 27 29 31 35 37 39 1 7 9 11 5 33 23 21 13 15 17 19 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 19 26 23 20 21 22 24 17 18 27 28 25 16 8 9 10 11 12 u4 ad1672 15 14 13 6 7 1 2 3 4 5 tp6 figure 31. evaluation board schematic obsolete
ad1672 rev. 0 C18C figure 32. pcb component side layout for evaluation board figure 33. pcb solder side layout for evaluation board obsolete
ad1672 rev. 0 C19C figure 34. pcb component side silkscreen figure 35. pcb ground plane layout for ad1672 obsolete
ad1672 rev. 0 C20C figure 36. pcb power plane layout for ad1672 outline dimensions dimensions shown in inches and (mm). 28-lead plcc (p-28a) 4 pin 1 identifier 5 26 25 11 12 19 18 top view (pins down) 0.495 (12.57) 0.485 (12.32) sq 0.456 (11.58) 0.450 (11.43) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.050 (1.27) bsc 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) c2049C10C7/95 printed in u.s.a. obsolete

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